High-speed CMOS switch designs for free-space optoelectronic MIN's

We present the theory, experimental results, and analytical modeling of high-speed CMOS switches, with a 2-D layout, suitable for the implementation of packet-switched free-space optoelectronic Multistage Interconnection Networks (MINs). These switches are fully connected, bi-directional, and scaleable. The first design is a proof of concept of the half-switch, which is a two-to-one multiplexer, and the 2-D layout. The second design introduces a novel self-routing concept, with contention detection and packet drop-and-resend capabilities. It uses three-valued logic, with 2.5V being the third value for a 5V power supply. Simulations show that for a 0.8 μm CMOS technology the switches can operate at speeds up to 250 Mbits/sec. Scaled-down versions of both designs have been successfully implemented in 2.0 μm CMOS. The analytical modeling of the switches show that large scale free-space optoelectronic MINs using this concept could offer close to Terabit/sec throughput capabilities and very reasonable power and area figures. For example, a 4096 channel system would offer 256 Gbits/sec aggregate throughput for a total silicon area of about 18 cm and a total power consumption (optics plus electronics) of about 90 W.